HD6417706 Datasheet, PDF (135/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

4.3 Operation
4.3.1 Reset
The reset sequence is used to power up or restart the SH7706 from the initialization state. The
RESETP signal and RESETM signal are sampled every clock cycle, and in the case of a power-on
reset, all processing being executed (excluding the RTC) is suspended, all unfinished events are
canceled, and reset processing is executed immediately. In the case of a manual reset, however,
reset processing is executed after memory access in progress is completed. The reset sequence
consists of the following operations:
1. The MD bit in SR is set to 1 to place the SH7706 in privileged mode.
2. The BL bit in SR is set to 1, masking any subsequent exceptions.
3. The RB bit in SR is set to 1.
4. An encoded value of H'000 in a power-on reset or H'020 in a manual reset is written to bits 11
to 0 of the EXPEVT register to identify the exception event.
5. Instruction execution jumps to the user-written exception handler at address H'A0000000.
4.3.2 Interrupts
An interrupt processing request is accepted on completion of the current instruction. The interrupt
acceptance sequence consists of the following operations:
1. The contents of the PC and SR are saved in SPC and SSR, respectively.
2. The BL bit in SR is set to 1, masking any subsequent exceptions.
3. The MD bit in SR is set to 1 to place the SH7706 in privileged mode.
4. The RB bit in SR is set to 1.
5. An encoded value identifying the exception event is written to bits 11 to 0 of the INTEVT and
INTEVT2 registers.
6. Instruction execution jumps to the vector location designated by the sum of the value of the
contents of the VBR and H'00000600 to invoke the exception handler.
Rev. 4.00, 03/04, page 89 of 660