HD6417706 Datasheet, PDF (344/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

10.4 Register Description
The CPG includes the following register. Refer to section 23, List of Registers, for more details of
the addresses and access sizes.
• Frequency control register (FRQCR)
10.4.1 Frequency Control Register (FRQCR)
The frequency control register (FRQCR) is a 16-bit read/write register used to specify, the
frequency multiplication ratio of PLL circuit 1, and the frequency division ratio of the internal
clock and the peripheral clock. Only word access can be used on the FRQCR register.
The FRQCR register is initialized to H'0102 at a power-on reset by the RESETP pin and retains its
previous value at a manual reset or in standby mode.
Bit
Bit Name Initial Value R/W Description
15
STC2
0
R/W Frequency Multiplication Ratio
5
STC1
0
4
STC0
0
R/W These bits specify the frequency multiplication ratio of
R/W ^{PLL circuit 1.}
000: × 1
001: × 2
100: × 3
010: × 4
Other than the above: Reserved (Setting prohibited)
Note: Do not set the output frequency of PLL circuit 1
higher than 133 MHz.
14
IFC2
0
R/W Internal Clock Frequency Division Ratio
3
IFC1
0
2
IFC0
0
R/W These bits specify the frequency division ratio (Divider
R/W ^{1)of the internal clock with respect to the output}
frequency of PLL circuit 1.
000: × 1
001: × 1/2
100: × 1/3
010: × 1/4
Other than the above: Reserved (Setting prohibited)
Note: Do not set the internal clock frequency lower
than the CKIO frequency.
Rev. 4.00, 03/04, page 298 of 660