HD6417706 Datasheet, PDF (207/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

8.2 Input/Output Pin
Table 8.1 lists the BSC pin configuration.
Table 8.1 Pin Configuration
Pin Name
Signal
I/O Description
Address bus
A25 to A0
O Address output
Data bus
D15 to D0
I/O Data I/O
D31 to D16 I/O When 32-bit bus width, data I/O
Bus cycle start
BS
O Shows start of bus cycle. During burst transfers, asserts
every data cycle.
Chip select 0, 2 to 4 CS0, CS2 to O Chip select signal to indicate area being accessed.
CS4
Chip select 5, 6
CS5/CE1A,
CS6/CE1B
O Chip select signal to indicate area being accessed.
CS5/CE1A and CS6/CE1B can also be used as CE1A
and CE1B of PCMCIA.
PCMCIA card select CE2A, CE2B O When PCMCIA is used, CE2A and CE2B
Read/write
RD/WR
O Data bus direction indicator signal. Synchronous DRAM
write indicator signal.
Row address strobe RASL
L
O When synchronous DRAM is used, RASL for lower 32-
Mbyte address.
Row address strobe RASU
U
O When synchronous DRAM is used, RASU for upper 32-
Mbyte address.
Column address
strobe
CASL
O When synchronous DRAM is used, CASL signal for
lower 32-Mbyte address.
Column address
strobe
CASU
O When synchronous DRAM is used, CASU signal for
upper 32-Mbyte address.
Data enable 0
WE0/DQMLL O
When memory other than synchronous DRAM is used,
selects D7 to D0 write strobe signal. When
synchronous DRAM is used, selects D7 to D0.
Data enable 1
WE1/DQMLU/ O
WE
When memory other than synchronous DRAM is used,
selects D15 to D8 write strobe signal. When
synchronous DRAM is used, selects D15 to D8. When
PCMCIA is used, strobe signal that indicates the write
cycle.
Data enable 2
WE2/DQMUL/ O
ICIORD
When memory other than synchronous DRAM is used,
selects D23 to D16 write strobe signal. When
synchronous DRAM is used, selects D23 to D16. When
PCMCIA is used, strobe signal indicating I/O read.
Rev. 4.00, 03/04, page 161 of 660