HD6417706 Datasheet, PDF (267/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

CKIO
Address
upper bits
A12 or A11 *¹
Address
lower bits *²
or
Tp
Tr
Tc1
Tc2
Tc3
Td4
RD/
D31 to D0
Notes: 1. Command bit
2. Column address
Figure 8.23 Burst Write Timing (Different Row Addresses)
• Refreshing
The bus state controller is provided with a function for controlling synchronous DRAM refreshing.
Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1
in MCR. If synchronous DRAM is not accessed for a long period, self-refresh mode, in which the
power consumption for data retention is low, can be activated by setting both the RMODE bit and
the RFSH bit to 1.
Rev. 4.00, 03/04, page 221 of 660