HD6417706 Datasheet, PDF (661/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

24.3.8 Peripheral Module Signal Timing
Table 24.8 Peripheral Module Signal Timing
Module
TMU,
RTC
SCI
Port
Item
Timer input setup time
Timer clock input setup time
Timer clock
pulse width
Edge specification
Both edge specification
Oscillation settling time
Input clock
cycle
Asynchronization
Clock synchronization
Input clock rise time
Input clock fall time
Input clock pulse width
Transmission data delay time
Receive data setup time
(clock synchronization)
Receive data hold time
(clock synchronization)
RTS delay time
CTS setup time
(clock synchronization)
CTS hold time
(clock synchronization)
Output data delay time
Input data setup time 1
Input data hold time 1
Input data setup time 2
Input data hold time 2
Input data setup time 3
DMAC
Input data hold time 3
DREQ setup time
DREQ hold time
DRAK delay time
Symbol
tTCLKS
tTCKS
tTCKWH
tTCKWL
tROSC
tSCYC
tSCKR
tSCKF
tSCKW
tTXD
tRXS
Min
15
15
1.5
2.5
—
4
6
—
—
0.4
—
100
Max Unit Figure
— ns 24.47
—
24.48
— tcyc
—
3
s
24.44
— tcyc 24.50,
—
24.51
1.5
24.50
1.5
0.6 tscyc
100 ns 24.51
—
tRXH
100 —
tRTSD
tCTSS
— 100
100 —
tCTSH
100 —
tPORTD
—
17
ns 24.52
tPORTS1
15
—
tPORTH1
8
—
tPORTS2
tcyc+ —
15
tPORTH2
tPORTS3
8
—
3×tcyc —
+15
tPORTH3
8
—
tDREQ
6
— ns 24.53
tDREQH
4
—
tDRAKD
—
10
22.54
Rev. 4.00, 03/04, page 615 of 660