HD6417706 Datasheet, PDF (317/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

CKIO
A25 to A0
Transfer
+4
source address
D31 to D0
+8
+12
DACKn
Figure 9.13 Example of DMA Transfer Timing in the Single Address Mode
(16- Byte Transfer, External Memory Space (Ordinary Memory) -> External Device with DACK)
Bus Modes: There are two bus modes: cycle-steal and burst. Select the mode in the TM bits of
CHCR_0 to CHCR_3 (one byte, word, or longword, or 16-byte data).
• Cycle-Steal Mode
In the cycle-steal mode, the bus right is given to another bus master after a one-transfer-unit
(8-, 16-, or 32-bit unit) DMA transfer. When another transfer request occurs, the bus rights are
obtained from the other bus master and a transfer is performed for one transfer unit. When that
transfer ends, the bus right is passed to the other bus master. This is repeated until the transfer
end conditions are satisfied.
In the cycle-steal mode, transfer areas are not affected regardless of settings of the transfer
request source, transfer source, and transfer destination. Figure 9.14 shows an example of
DMA transfer timing in the cycle steal mode. Transfer conditions shown in the figure are:
 Dual address mode
 DREQ level detection
Bus right returned to CPU
Bus cycle
CPU
CPU
CPU
DMAC DMAC
Read Write
CPU
DMAC
Read
DMAC
Write
CPU
CPU
Figure 9.14 DMA Transfer Example in the Cycle-Steal Mode
Rev. 4.00, 03/04, page 271 of 660