HD6417706 Datasheet, PDF (442/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

14.5 SCI Interrupt Sources
The SCI has four interrupt sources in each channel: Transmit-end (TEI), receive-error (ERI),
receive-data-full (RXI), and transmit-data-empty (TXI). Table 14.12 lists the interrupt sources and
indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE
bits in SCSCR. Each interrupt request is sent separately to the interrupt controller.
TXI is requested when the TDRE bit in the SCSSR is set to 1.
RXI is requested when the RDRF bit in the SCSSR is set to 1.
ERI is requested when the ORER, PER, or FER bit in the SCSSR is set to 1.
TEI is requested when the TEND bit in the SCSSR is set to 1. Where the TXI interrupt indicates
that transmit data writing is enabled, the TEI interrupt indicates that the transmit operation is
complete.
Table 14.12 SCI Interrupt Sources
Interrupt Source
ERI
RXI
TXI
TEI
Description
Priority When Reset Is Cleared
Receive error (ORER, PER, or FER) High
Receive data full (RDRF)
Transmit data empty (TDRE)
Transmit end (TEND)
Low
See section 4, Exception Processing, for information on the priority order and relationship to non-
SCI interrupts.
Rev. 4.00, 03/04, page 396 of 660