HD6417706 Datasheet, PDF (343/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Clock
Mode FRQCR PLL1
PLL2
Clock Rate*
CKIO Frequency
(I:B:P)
Input Frequency Range Range
7
H'0100 ON (× 1) OFF
1:1:1
25 MHz to 33.34 MHz 25 MHz to 33.34 MHz
H'0101 ON (× 1) OFF
1:1:1/2
25 MHz to 66.67 MHz 25 MHz to 66.67 MHz
H'0102 ON (× 1) OFF
1:1:1/4
25 MHz to 66.67 MHz 25 MHz to 66.67 MHz
H'0111 ON (× 2) OFF
2:1:1
25 MHz to 33.34 MHz 25 MHz to 33.34 MHz
H'0112 ON (× 2) OFF
2:1:1/2
25 MHz to 66.67 MHz 25 MHz to 66.67 MHz
H'0115 ON (× 2) OFF
1:1:1
25 MHz to 33.34 MHz 25 MHz to 33.34 MHz
H'0116 ON (× 2) OFF
1:1:1/2
25 MHz to 66.67 MHz 25 MHz to 66.67 MHz
H'0122 ON (× 4) OFF
4:1:1
25 MHz to 33.34 MHz 25 MHz to 33.34 MHz
H'0126 ON (× 4) OFF
2:1:1
25 MHz to 33.34 MHz 25 MHz to 33.34 MHz
H'012A ON (× 4) OFF
1:1:1
25 MHz to 33.34 MHz 25 MHz to 33.34 MHz
H'A100 ON (× 3) OFF
3:1:1
25 MHz to 33.34 MHz 25 MHz to 33.34 MHz
H'A101 ON (× 3) OFF
3:1:1/2
25 MHz to 44.44 MHz 25 MHz to 44.44 MHz
H'E100 ON (× 3) OFF
1:1:1
25 MHz to 33.34 MHz 25 MHz to 33.34 MHz
H'E101 ON (× 3) OFF
1:1:1/2
25 MHz to 44.44 MHz 25 MHz to 44.44 MHz
Note: * Taking input clock as 1
Max. frequency: Iφ = 133.34 MHz, Bφ (CKIO) = 66.67 MHz, Pφ = 33.34 MHz
Cautions:
1. The input to divider 1 is the output of the PLL circuit 1:
• When PLL circuit 1 is on.
2. The input of divider 2 is the output of the PLL circuit 1.
3. The frequency of the internal clock (Iφ):
• The frequency of the internal clock (Iφ) is the product of the frequency of the CKIO
pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider
1 when PLL circuit 1 is on.
• Do not set the internal clock frequency lower than the CKIO pin frequency.
4. The frequency of the peripheral clock (Pφ):
• The frequency of the peripheral clock (Pφ) is the product of the frequency of the CKIO
pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 2.
• The peripheral clock frequency should not be set higher than the frequency of the CKIO
pin, higher than 33 MHz, or lower than 1/8 the internal clock (Iφ).
5. The output frequency of PLL circuit 1 is the product of the CKIO frequency and the
multiplication ratio of PLL circuit 1.
6. × 1, × 2, × 3, or × 4 can be used as the multiplication ratio of PLL circuit 1. × 1, × 1/2, × 1/3,
and × 1/4 can be selected as the division ratios of dividers 1 and 2. Set the rate in the frequency
control register. The on/off state of PLL circuit 2 and the multiplication ratio are determined by
the mode.
Rev. 4.00, 03/04, page 297 of 660