HD6417706 Datasheet, PDF (406/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
5
ORER
0
R/(W)*
Overrun Error
Indicates that data reception aborted due to an
overrun error.
0: Receiving is in progress or has ended
normally*¹
[Clearing conditions]
1. The chip is reset or enters standby mode.
2. ORER is read as 1, then written to with 0.
1: A receive overrun error occurred*²
[Setting condition]
Reception of the next serial data has ended
when RDRF is set to 1.
Notes: 1. Clearing the RE bit to 0 in the serial
control register does not affect the
ORER bit, which retains its previous
value.
2. SCRDR continues to hold the data
received before the overrun error, so
subsequent receive data is lost. Serial
receiving cannot continue while ORER is
set to 1. In the clock synchronous mode,
serial transmitting is also disabled.
Rev. 4.00, 03/04, page 360 of 660