HD6417706 Datasheet, PDF (178/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

6.6 Interrupt Response Time
The time from generation of an interrupt request until interrupt exception processing is performed
and fetching of the first instruction of the exception handler is started (the interrupt response time)
is shown in table 6.7. Figure 6.4 shows an example of pipeline operation when an IRL interrupt is
accepted. When SR.BL is 1, interrupt exception processing is masked, and is kept waiting until
completion of an instruction that clears BL to 0.
The response time is represented by the clock number of Iφ. Depending on the Pφ phase when an
interrupt is occurred, one clock period of Pφ may vary from the contents of this table.
Table 6.7 Interrupt Response Time
Number of States
Item
Peripheral
NMI
IRQ
IRL
Modules
Notes
Time for priority 0.5 × Icyc 1.5 × Icyc
decision and SR + 1.5 × Bcyc + 0.5 × Bcyc
mask bit
+ 2 × Pcyc*²
comparison
0.5 × Icyc
+ 0.5 × Bcyc
+ 3.5 × Pcyc
0.5 × Icyc
+ 1.5 × Pcyc*³
0.5 × Icyc
+ 3 × Pcyc*⁴
Wait time until X (≥ 0) × Icyc X (≥ 0) × Icyc
end of sequence
being executed
by CPU
X (≥ 0) × Icyc X (≥ 0) × Icyc
Interrupt exception processing is
kept waiting until the executing
instruction ends. If the number of
instruction execution states is S*¹,
the maximum wait time is: X = S –
1. However, if BL is set to 1 by
instruction execution or by an
exception, interrupt exception
processing is deferred until
completion of an instruction that
clears BL to 0. If the following
instruction masks interrupt
exception processing, the
processing may be further
deferred.
Time from
5 × Icyc
interrupt
exception
processing (save
of SR and PC)
until fetch of first
instruction of
exception service
routine is started
5 × Icyc
5 × Icyc
5 × Icyc
Rev. 4.00, 03/04, page 132 of 660