HD6417706 Datasheet, PDF (549/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

19.5 Access Size of A/D Data Register
19.5.1 Word Access
When A/D data registers (ADDRA to ADDRD) are read in word, A/D data register values are
read from bits 15 to 8, and invalid data is read from bits 7 to 0.
Figure 19.3 shows an example of reading ADDRAH.
15
87
0
ADDRAH
Invalid data
Figure 19.3 Word Access Example
19.5.2 Longword Access
When A/D data registers are read in longword, the upper byte of the A/D data register is read from
bits 31 to 24, invalid data from bits 23 to 16, the lower byte of the A/D data register from bits 15
to 8, and invalid data from bits 7 to 0.
Figure 19.4 shows an example of reading ADDRAH.
31
24 23
16 15
87
0
ADDRAH
Invalid data
ADDRAL
Invalid data
Figure 19.4 Longword Access Example
19.6 Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has two
operating modes: single mode and scan mode.
19.6.1 Single Mode (MULTI = 0)
Single mode should be selected when only one A/D conversion on one channel is required. A/D
conversion starts when the ADST bit in ADCSR is set to 1 by software, or by external trigger
input. The ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0
when conversion ends.
When conversion ends the ADF bit is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is
requested at this time. To clear the ADF flag to 0, first read ADCSR, then write 0 in ADF.
Rev. 4.00, 03/04, page 503 of 660