HD6417706 Datasheet, PDF (187/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

7.2.8 Break Bus Cycle Register B (BBRB)
Break bus cycle register B (BBRB) is a 16-bit read/write register, which specifies, (1) CPU cycle
or DMAC cycle, (2) instruction fetch or data access, (3) read/write, and (4) operand size in the
break conditions of channel B.
Bit
15 to 8
7
6
5
4
3
2
Bit Name Initial Value
—
All 0
CDB1
0
CDB0
0
IDB1
0
IDB0
0
RWB1
0
RWB0
0
R/W Description
R Reserved
These bits are always read as 0. These bits are
always read as 0.
R/W CPU Cycle/DMAC Cycle Select B
R/W Select the CPU cycle or DMAC cycle as the bus
cycle of the channel B break condition.
00: Condition comparison is not performed
X1: The break condition is the CPU cycle
10: The break condition is the DMAC cycle
R/W Instruction Fetch/Data Access Select B
R/W Select the instruction fetch cycle or data access
cycle as the bus cycle of the channel B break
condition.
00: Condition comparison is not performed
01: The break condition is the instruction fetch cycle
10: The break condition is the data access cycle
11: The break condition is the instruction fetch cycle
or data access cycle
R/W Read/Write Select B
R/W Select the read cycle or write cycle as the bus cycle
of the channel B break condition.
00: Condition comparison is not performed
01: The break condition is the read cycle
10: The break condition is the write cycle
11: The break condition is the read cycle or write
cycle
Rev. 4.00, 03/04, page 141 of 660