HD6417706 Datasheet, PDF (463/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Base clock
372 clock cycles
186 clock cycles
0
185
Receive
data (RxD)
Synchro-
nization
sampling
timing
Start
bit
371 0
185
D0
371 0
D1
Data
sampling
timing
Figure 15.8 Receive Data Sampling Timing in Smart Card Mode
The receive margin is found from the following equation:
For smart card mode:
M = (0.5 – ¹ ) – (L – 0.5)F – ^{D – 0.5} (1 + F) × 100%
2N
N
Where:
M = Receive margin (%)
N = Ratio of bit rate to clock (N = 372)
D = Clock duty (D = 0 to 1.0)
L = Frame length (L = 10)
F = Absolute value of clock frequency deviation
Using this equation, the receive margin when F = 0 and D = 0.5 is as follows:
When D = 0.5 and F = 0:
M = (0.5 – 1/2 × 372) × 100% = 49.866%
Rev. 4.00, 03/04, page 417 of 660