HD6417706 Datasheet, PDF (188/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value
1
SZB1
0
0
SZB0
0
Note: X: Don't care
R/W Description
R/W Operand Size Select B
R/W Select the operand size of the bus cycle for the
channel B break condition.
00: The break condition does not include operand
size
01: The break condition is byte access
10: The break condition is word access
11: The break condition is longword access
7.2.9 Break Control Register (BRCR)
BRCR sets the following conditions:
1. Channels A and B are used in two independent channels condition or under the sequential
condition.
2. A break is set before or after instruction execution.
3. A break is set by the number of execution times.
4. Determine whether to include data bus on channel B in comparison conditions.
5. Enable PC trace.
6. Enable the ASID check.
The break control register (BRCR) is a 32-bit read/write register that has break conditions match
flags and bits for setting a variety of break conditions.
Bit
31 to 22
21
Bit Name
—
BASMA
Initial Value R/W
All 0
R
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Break ASID Mask A
Specifies whether the bits of the channel A break
ASID7 to ASID0 (BASA7 to BASA0) set in BASRA
are masked or not.
0: All BASRA bits are included in break condition,
ASID is checked
1: No BASRA bits are included in break condition,
ASID is not checked
Rev. 4.00, 03/04, page 142 of 660