HD6417706 Datasheet, PDF (169/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

6.4.3 Interrupt Control Register 1 (ICR1)
The interrupt control register 1 (ICR1) is a 16-bit register that specifies the detection mode to
external interrupt input pins, IRQ0 to IRQ5 individually: rising edge, falling edge, or low level.
Bit
Bit Name Initial Value R/W Description
15
MAI
0
R/W Mask All Interrupts
When set to 1, masks all interrupt requests when a
low level is being input to the NMI pin. Masks NMI
interrupts in standby mode.
0: All interrupt requests are not masked when a low
level is being input to the NMI pin
1: All interrupt requests are masked when a low level
is being input to the NMI pin
14
IRQLVL 1
R/W Interrupt Request Level Detect
Selects whether the IRQ3 to IRQ0 pins are used as
four independent interrupt pins or as 15-level interrupt
pins encoded as IRL3 to IRL0.
0: Used as four independent interrupt request pins
IRQ3 to IRQ0
1: Used as encoded 15-level interrupt pins as IRL3 to
IRL0
13
BLMSK 0
R/W BL Bit Mask
Specifies whether NMI interrupts are masked when
the BL bit of the SR register is 1.
0: NMI interrupts are masked when the BL bit is 1
1: NMI interrupts are accepted regardless of the BL
bit setting
12
—
0
R Reserved
This bit is always read as 0. The write value should
always be 0.
11
IRQ51S 0
R/W IRQ5 Sense Select
10
IRQ50S 0
R/W Select whether the interrupt signal to the IRQ5 pin is
detected at the rising edge, at the falling edge, or at
low level.
00: An interrupt request is detected at IRQ5 input
falling edge
01: An interrupt request is detected at IRQ5 input
rising edge
10: An interrupt request is detected at IRQ5 input low
level
11: Reserved (Setting prohibited)
Rev. 4.00, 03/04, page 123 of 660