HD6417706 Datasheet, PDF (274/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

CKIO
T1
TW
TW
TB2
TB1
TW
TB2 TB1
T2
A25 to A4
A3 to A0
CSn
RD/WR
RD
D31 to
D0
BS
WAIT
Note: For a write cycle, a basic bus cycle (write cycle) is performed.
Figure 8.28 Burst ROM Wait Access Timing
Rev. 4.00, 03/04, page 228 of 660