HD6417706 Datasheet, PDF (185/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W
5
IDA1
0
R/W
4
IDA0
0
R/W
3
RWA1
0
R/W
2
RWA0
0
R/W
1
SZA1
0
R/W
0
SZA0
0
R/W
Note: X Don't care
Description
Instruction Fetch/Data Access Select A
Selects the instruction fetch cycle or data access
cycle as the bus cycle of the channel A break
condition.
00: Condition comparison is not performed
01: The break condition is the instruction fetch
cycle
10: The break condition is the data access cycle
11: The break condition is the instruction fetch
cycle or data access cycle
Read/Write Select A
Selects the read cycle or write cycle as the bus
cycle of the channel A break condition.
00: Condition comparison is not performed
01: The break condition is the read cycle
10: The break condition is the write cycle
11: The break condition is the read cycle or write
cycle
Operand Size Select A
Selects the operand size of the bus cycle for the
channel A break condition.
00: The break condition does not include
operand size
11: The break condition is byte access
10: The break condition is word access
11: The break condition is longword access
7.2.4 Break Address Register B (BARB)
BARB is a 32-bit read/write register. BARB specifies the address used as a break condition in
channel B.
Bit
31 to 0
Bit Name
BAB31 to
BAB0
Initial Value R/W
All 0
R/W
Description
Break Address
Stores the address of LAB or IAB that specifies the
break conditions of channel B.
Rev. 4.00, 03/04, page 139 of 660