HD6417706 Datasheet, PDF (338/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

CAP1
CKIO
Cycle = Bcyc
CAP2
XTAL
EXTAL
Crystal
oscillator
Clock pulse generator
PLL circuit 1
(× 1, 2, 3, 4)
PLL circuit 2
(× 1, 4)
Divider 1
×1
× 1/2
× 1/3
× 1/4
Divider 2
×1
× 1/2
× 1/3
× 1/4
× 1/6
Internal
clock (Iφ)
Cycle = Icyc
Peripheral
clock (Pφ)
Cycle = Pcyc
Bus clock (Bφ)
Cycle = Bcyc
MD2
MD1
MD0
CPG control unit
Clock frequency
control circuit
Standby control
circuit
FRQCR
STBCR
Standby
control
Bus interface
Legend
FRQCR: Frequency control register
STBCR: Standby control register
Internal bus
Figure 10.1 Block Diagram of Clock Pulse Generator
Rev. 4.00, 03/04, page 292 of 660