HD6417706 Datasheet, PDF (554/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

19.6.4 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time t_D after the ADST bit in ADCSR is set to 1, then starts conversion. Figure 19.8
shows the A/D conversion timing. Table 19.3 indicates the A/D conversion time.
As indicated in figure 19.8, the A/D conversion time includes t_D and the input sampling time. The
length of t_D varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 19.3.
In multi mode and scan mode, the values given in table 19.3 apply to the first conversion. In the
second and subsequent conversions the conversion time is fixed at 512 states when CKS = 0 or
256 states when CKS = 1.
*¹
Pφ
Address
Write
signal
Input sampling
timing
ADF
*²
t_D
t_SPL
t_CONV
t_D : A/D conversion start delay
t_SPL : Input sampling time
t_CONV : A/D conversion time
Notes: 1. ADCSR write cycle
2. ADCSR address
Figure 19.8 A/D Conversion Timing
Rev. 4.00, 03/04, page 508 of 660