HD6417706 Datasheet, PDF (332/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

• Compare Match Flag Set Timing
The CMF bit of the CMCSR register is set to 1 by the compare match signal generated when the
CMCOR register and the CMCNT counter match. The compare match signal is generated upon the
final state of the match (timing at which the CMCNT counter matching count value is updated).
Consequently, after the CMCOR register and the CMCNT counter match, a compare match signal
will not be generated until a CMCNT counter input clock occurs. Figure 9.29 shows the CMF bit
set timing.
CK
CMCNT
input clock
CMCNT
N
0
CMCOR
N
Compare
match signal
CMF
CMI
Figure 9.29 CMF Set Timing
• Compare Match Flag Clear Timing
The CMF bit of the CMCSR register is cleared by writing 0 to it after reading 1. Figure 9.30 shows
the timing when the CMF bit is cleared by the CPU.
CMCSR0 write cycle
T₁
T₂
CK
CMF
Figure 9.30 Timing of CMF Clear by the CPU
Rev. 4.00, 03/04, page 286 of 660