HD6417706 Datasheet, PDF (484/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
0
DR
0
R/(W)* Receive Data Ready
Indicates that the SCFRDR2 stores the data
which is less than the specified number of receive
triggers, and that next data is not yet received
after 15 etu has elapsed from the last stop bit.
0: Receive is in progress, or no received data
remains in SCFRDR2 after the receive ended
normally.
[Clearing conditions]
1. The chip is power-on reset or enters
standby mode.
2. DR is read as 1, then written to with 0.
1: Next receive data is not received.
[Setting condition]
SCFRDR2 stores the data which is less than
the specified number of receive triggers, and
that next data is not yet received after 15 etu
has elapsed from the last stop bit.*
Note: * This is equivalent to 1.5 frames with the
8-bit 1-stop-bit format. (etu: Elementary
Time Unit)
Note: * The only value that can be written is 0 to clear the flag.
Rev. 4.00, 03/04, page 438 of 660