HD6417706 Datasheet, PDF (77/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Classification Types
Arithmetic
21
operations
Logic
6
operations
Shift
12
Operation
Code
Function
No. of
Instructions
MUL
Double-precision multiplication (32 × 32 bits) 33
MULS
Signed multiplication (16 × 16 bits)
MULU
Unsigned multiplication (16 × 16 bits)
NEG
Negation
NEGC
Negation with borrow
SUB
Binary subtraction
SUBC
Binary subtraction with borrow
SUBV
Binary subtraction with underflow check
AND
Logical AND
14
NOT
Bit inversion
OR
Logical OR
TAS
Memory test and bit set
TST
Logical AND and T bit set
XOR
Exclusive OR
ROTL
One-bit left rotation
16
ROTR
One-bit right rotation
ROTCL One-bit left rotation with T bit
ROTCR One-bit right rotation with T bit
SHAL
One-bit arithmetic left shift
SHAR
One-bit arithmetic right shift
SHLL
One-bit logical left shift
SHLLn
n-bit logical left shift
SHLR
One-bit logical right shift
SHLRn n-bit logical right shift
SHAD
Dynamic arithmetic shift
SHLD
Dynamic logical shift
Rev. 4.00, 03/04, page 31 of 660