HD6417706 Datasheet, PDF (158/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Figure 6.1 is a block diagram of the INTC.
IRQOUT
NMI
IRL3 to IRL0
IRQ0 to IRQ5
DMAC
SCIF
SCI
ADC
TMU
RTC
WDT
REF
H-UDI
Input
4
control
6
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request/
refresh request)
(Interrupt request)
Priority
identifier
Com-
parator
IPR
ICR
IPRA to IPRE
Bus
interface
Legend
TMU:
RTC:
SCI:
SCIF:
WDT:
REF:
ICR:
IPRA-IPRE:
SR:
DMAC:
ADC:
H-UDI:
Timer unit
Realtime clock unit
Serial communication interface
Serial communication interface (with FIFO)
Watchdog timer
Refresh requests in the bus state controller
Interrupt control register
Registers A-E for setting the interrupt proprity levels
Status register
Direct memory access controller
Analog-to-digital converter
User debugging interface
INTC
Figure 6.1 INTC Block Diagram
Interrupt
request
SR
3210
CPU
Rev. 4.00, 03/04, page 112 of 660