HD6417706 Datasheet, PDF (259/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

• Burst Write
The timing chart for a burst write is shown in figure 8.16. In this LSI, a burst write occurs only in
the event of cache write-back or 16-byte transfer by DMAC. In a burst write operation, following
the Tr cycle in which ACTV command output is performed, a WRIT command is issued in the
Tc1, Tc2, and Tc3 cycles, and a WRITA command that performs auto-precharge is issued in the
Tc4 cycle. In the write cycle, the write data is output at the same time as the write command. In
case of the write with auto-precharge command, precharging of the relevant bank is performed in
the synchronous DRAM after completion of the write command, and therefore no command can
be issued for the same bank until precharging is completed. Consequently, in addition to the
precharge wait cycle, Tpc, used in a read access, cycle Trwl is also added as a wait interval until
precharging is started following the write command. Issuance of a new command for the same
bank is postponed during this interval. The number of Trwl cycles can be specified by the TRWL
bit in MCR.
CKIO
Address
upper bits
Tr
Tc1
Tc2
Tc3
Tc4 (Trw1)
(Tpc)
A12 or A11 *¹
Address
lower bits *²
RD/
D31 to D0
(read)
Notes: 1. Command bit
2. Column address
Figure 8.16 Basic Timing for Synchronous DRAM Burst Write
Rev. 4.00, 03/04, page 213 of 660