HD6417706 Datasheet, PDF (232/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit*
Bit Name Initial Value R/W
10
A6TED2 0
R/W
5
A6TED1 0
R/W
4
A6TED0 0
R/W
9
A5TEH2 0
R/W
3
A5TEH1 0
R/W
2
A5TEH0 0
R/W
8
A6TEH2 0
R/W
1
A6TEH1 0
R/W
0
A6TEH0 0
R/W
Note: * The bit numbers are out of sequence.
Description
Area 6 Address OE/WE Assert Delay
The A6TED bits specify the address to OE/WE
assert delay time for the PCMCIA interface
connected to area 6.
000: 0.5-cycle delay
001: 1.5-cycle delay
010: 2.5-cycle delay
011: 3.5-cycle delay
100: 4.5-cycle delay
101: 5.5-cycle delay
110: 6.5-cycle delay
111: 7.5-cycle delay
Area 5 OE/WE Negate Address Delay
The A5TEH bits specify the OE/WE negate
address delay time for the PCMCIA interface
connected to area 5.
000: 0.5-cycle delay
001: 1.5-cycle delay
010: 2.5-cycle delay
011: 3.5-cycle delay
100: 4.5-cycle delay
101: 5.5-cycle delay
110: 6.5-cycle delay
111: 7.5-cycle delay
Area 6 OE/WE Negate Address Delay
The A6TEH bits specify the OE/WE negate
address delay time for the PCMCIA interface
connected to area 6.
000: 0.5-cycle delay
001: 1.5-cycle delay
010: 2.5-cycle delay
011: 3.5-cycle delay
100: 4.5-cycle delay
101: 5.5-cycle delay
110: 6.5-cycle delay
111: 7.5-cycle delay
Rev. 4.00, 03/04, page 186 of 660