HD6417706 Datasheet, PDF (481/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
4
BRK
0
R/(W)* Break Detection
Indicates that a break signal is detected in
received data.
0: No break signal is being received.
[Clearing conditions]
1. The chip is power-on reset or enters
standby mode.
2. BRK is read as 1, then written to with 0.
1: A break signal is received.
[Setting conditions]
1. Data including a framing error is received.
2. A framing error with space 0 occurs in the
subsequent received data.
Note: When a break is detected, transfer of the
received data (H'00) to SCFRDR2 stops
after detection. When the break ends and
the receive signal becomes mark 1, the
transfer of the received data resumes. The
received data of a frame in which a break
signal is detected is transferred to
SCFRDR2. After this, however, no
received data is transferred until a break
ends with the received signal being mark 1
and the next data is received.
3
FER
0
R
Framing Error
Indicates a framing error in the data read from the
SCFRDR2.
0: No framing error occurred in the data read from
SCFRDR2.
[Clearing conditions]
1. The chip is power-on reset or enters
standby mode.
2. No framing error is present in the data read
from SCFRDR2.
1: A framing error occurred in the data read from
SCFRDR2.
[Setting condition]
A framing error is present in the data read from
SCFRDR2
Rev. 4.00, 03/04, page 435 of 660