HD6417706 Datasheet, PDF (217/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
8
A5BST1 0
R/W Area 5 Burst Enable
7
A5BST0 0
R/W Specify whether to use burst ROM and PCMCIA burst
mode in physical space area 5. When burst ROM and
PCMCIA burst mode are used, set the number of burst
transfers.
00: Access area 5 as ordinary memory
01: Burst access of area 5 (4 consecutive accesses).
Can be used when bus width is 8, 16, or 32.
10: Burst access of area 5 (8 consecutive accesses).
Can be used when bus width is 8 or 16.
11: Burst access of area 5 (16 consecutive accesses).
Can be used only when bus width is 8.
6
A6BST1 0
R/W Area 6 Burst Enable
5
A6BST0 0
R/W Specify whether to use burst ROM and PCMCIA burst
mode in physical space area 6. When burst ROM and
PCMCIA burst mode are used, set the number of burst
transfers.
00: Access area 6 as ordinary memory
01: Burst access of area 6 (4 consecutive accesses).
Can be used when bus width is 8, 16, or 32.
10: Burst access of area 6 (8 consecutive accesses).
Can be used when bus width is 8 or 16.
11: Burst access of area 6 (16 consecutive accesses).
Can be used only when bus width is 8.
4
DRAMTP2 0
R/W Area 2, Area 3 Memory Type
3
DRAMTP1 0
2
DRAMTP0 0
R/W Designate the types of memory connected to physical
R/W ^{space areas 2 and 3. Ordinary memory, such as ROM,}
SRAM, or flash ROM, can be directly connected.
Synchronous DRAM can also be directly connected.
000: Areas 2 and 3 are ordinary memory
001: Reserved (Setting prohibited)
010: Area 2: ordinary memory; area 3: synchronous
DRAM*³
011: Areas 2 and 3 are synchronous DRAM*² *³
100: Reserved (Setting prohibited)
101: Reserved (Setting prohibited)
110: Reserved (Setting prohibited)
111: Reserved (Setting prohibited)
Rev. 4.00, 03/04, page 171 of 660