HD6417706 Datasheet, PDF (295/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W
Description
16
AL
0
(R/W)*² Acknowledge Level
AL specifies the DACK (acknowledge) signal output
is high active or low active.
This bit is only valid in CHCR_0 and CHCR_1.
Writing to this bit is invalid in CHCR_2 and CHCR_3;
0 is read if this bit is read.
0: Low-active output of DACK
1: High-active output of DACK
15
DM1
0
R/W
Destination Address Mode
14
DM0
0
R/W
DM1 and DM0 select whether the DMA destination
address is incremented, decremented, or left fixed.
00: Fixed destination address (Initial value)
01: Destination address is incremented (+1 in 8-bit
transfer, +2 in 16-bit transfer, +4 in 32-bit
transfer, +16 in 16-byte transfer)
10: Destination address is decremented (–1 in 8-bit
transfer, –2 in 16-bit transfer, –4 in 32-bit transfer;
illegal setting in 16-byte transfer)
11: Reserved (Setting prohibited)
13
SM1
0
R/W
Source Address Mode
12
SM0
0
R/W
SM1 and SM0 select whether the DMA source
address is incremented, decremented, or left fixed.
00: Fixed source address
01: Source address is incremented (+1 in 8-bit
transfer, +2 in 16-bit transfer, +4 in 32-bit
transfer, +16 in 16-byte transfer)
10: Source address is decremented (–1 in 8-bit
transfer, –2 in 16-bit transfer, –4 in 32-bit transfer;
illegal setting in 16-byte transfer)
11: Reserved (Setting prohibited)
Notes: If the transfer source is specified in indirect
address, specify the address, in which the
data to be transferred is stored and which is
stored as data (indirect address), SAR_3.
Specification of SAR_3 increment or
decrement in indirect address mode depends
on SM1 and SM0 settings. In this case,
however, the SAR_3 increment or decrement
value is +4, –4, or fixed to 0 regardless of the
transfer data size specified in TS1 and TS0.
Rev. 4.00, 03/04, page 249 of 660