HD6417706 Datasheet, PDF (70/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Addressing Instruction
Mode
Format Effective Address Calculation Method
Calculation Formula
Register
@(disp:4,
indirect with Rn)
displacement
Effective address is register Rn contents with Byte: Rn + disp
4-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2
(word), or 4 (longword), according to the
operand size.
Word: Rn + disp × 2
Longword: Rn + disp ×
4
Rn
disp
+
(zero-extended)
×
Rn
+ disp × 1/2/4
Indexed
register
indirect
1/2/4
@(R0, Rn) Effective address is sum of register Rn and
R0 contents.
Rn
Rn + R0
+
Rn + R0
GBR indirect @(disp:8,
with
GBR)
displacement
R0
Effective address is register GBR contents Byte: GBR + disp
with 8-bit displacement disp added. After disp _{Word: GBR + disp × 2}
is zero-extended, it is multiplied by 1 (byte), 2
(word), or 4 (longword), according to the
Longword: GBR + disp
operand size.
×4
GBR
disp
+
(zero-extended)
×
GBR
+ disp × 1/2/4
Indexed GBR @(R0,
indirect
GBR)
1/2/4
Effective address is sum of register GBR and GBR + R0
R0 contents.
GBR
+
GBR + R0
R0
Rev. 4.00, 03/04, page 24 of 660