HD6417706 Datasheet, PDF (223/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

8.4.4 Wait State Control Register 2 (WCR2)
Wait state control register 2 (WCR2) is a 16-bit read/write register that specifies the number of
wait state cycles inserted for each area. It also specifies the pitch of data access for burst memory
accesses. This allows direct connection of even low-speed memories without an external circuit.
Bit
Bit Name Initial Value R/W Description
15
A6W2
1
R/W Area 6 Wait Control
14
A6W1
1
13
A6W0
1
R/W Specify the number of wait states inserted into
R/W ^{physical space area 6. Also specify the burst pitch for}
burst transfer.
Refer to table 8.6 for details.
12
A5W2
1
R/W Area 5 Wait Control
11
A5W1
1
10
A5W0
1
R/W Specify the number of wait states inserted into
R/W ^{physical space area 5. Also specify the burst pitch for}
burst transfer.
Refer to table 8.7 for details.
9
A4W2
1
R/W Area 4 Wait Control
8
A4W1
1
7
A4W0
1
R/W Specify the number of wait states inserted into
R/W ^{physical space area 4.}
Refer to table 8.8 for details.
6
A3W1
1
R/W Area 3 Wait Control
5
A3W0
1
R/W Specify the number of wait states inserted into
physical space area 3.
• For Ordinary memory
Inserted Wait States
WAIT Pin
00:
0
Ignored
01:
1
Enable
10:
2
Enable
11:
3
Enable
• For Synchronus DRAM
Synchronus DRAM :CAS Latency
00:
1
01:
1
10:
2
11:
3
Rev. 4.00, 03/04, page 177 of 660