HD6417706 Datasheet, PDF (367/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

2. External Clock Operation: Set the TPSC2 to TPSC0 bits in TCR to select the external clock
(TCLK) as the timer clock. Use the CKEG1 and CKEG0 bits in TCR to select the detection
edge. Rise, fall or both may be selected. The pulse width of the external clock must be at least
1.5 peripheral module clock cycles for single edges or 2.5 peripheral module clock cycles for
both edges. A shorter pulse width will result in accurate operation. Figure 12.5 shows the
timing for both-edge detection.
Pφ
External
clock input
pin (TCLK)
TCNT
input clock
TCNT
N+1
N
N–1
Figure 12.5 Count Timing when External Clock is Operating (Both Edges Detected)
3. On-Chip RTC Clock Operation: Set the TPSC2 to TPSC0 bits in TCR to select the on-chip
RTC clock as the timer clock. Figure 12.6 shows the timing.
RTC output
clock
TCNT input
clock
TCNT N + 1
N
N–1
Figure 12.6 Count Timing when On-Chip RTC Clock Is Operating
Rev. 4.00, 03/04, page 321 of 660