HD6417706 Datasheet, PDF (322/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

1st sampling
CKIO
2nd sampling
3rd sampling
DRAK
(High active)
Bus cycle
DACK
CPU
DMAC(Read)
DMAC(Write)
CPU
DMAC(Read)
Figure 9.17 Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles)
DMAC(Write)
1st sampling
CKIO
2nd sampling
3rd sampling
DRAK
(High active)
Bus cycle
DACK
CPU
DMAC(Read)
DMAC(Write)
CPU
DMAC(Read)
Figure 9.18 Cycle-Steal Mode, Level Input (CPU Access: 3 Cycles)
1st sampling 2nd sampling
CKIO
3rd sampling
DRAK
(High active)
Bus cycle
DACK
(RD output)
CPU
DMAC(Read)
DMAC(Write)
CPU
DMAC(Read)
Figure 9.19 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DMA RD Access: 4
Cycles)
Rev. 4.00, 03/04, page 276 of 660