HD6417706 Datasheet, PDF (311/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

CKIO
A25 to A0
Transfer
+4
source address
D31 to D0
+8
+12
Transfer
+4
destination address
+8
+12
DACKn
Data read cycle
(1st cycle)
(2nd cycle)
Note: Transfer between external memories, DACK output in a read cycle DACK output timing
is the same as that of .
Figure 9.7 Example of DMA Transfer Timing in the Direct Address Mode
in the Dual Address Mode
(16-byte Transfer, Transfer Source: Ordinary Memory, Transfer Destination: Ordinary
Memory)
CKIO
A25 to A0
+4
Transfer source address
Transfer destination address
+8
+12
D31 to D0
RD/
DACKn
Data read cycle
(2nd cycle)
(1st cycle)
Data write cycle
Note: Transfer between external memories, DACK output in a read cycle DACK output timing
is the same as that of .
Figure 9.8 Example of DMA Transfer Timing in the Direct Address Mode
in the Dual Address Mode
(16-byte Transfer, Transfer Source: Synchronous DRAM, Transfer Destination: Ordinary
Memory)
Rev. 4.00, 03/04, page 265 of 660