HD6417706 Datasheet, PDF (318/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

• Burst Mode
In the burst mode, once the bus right is obtained, the transfer is performed continuously without
passing it until the transfer end conditions are satisfied. In the external request mode with low
level detection of the DREQ pin, however, when the DREQ pin is driven high, the bus is
passed to the other bus master after the DMAC transfer request that has already been accepted
ends, even if the transfer end conditions have not been satisfied.
The burst mode cannot be used when the serial communications interface (SCIF) and A/D
converter are the transfer request sources. Figure 9.15 shows a timing at this point.
Bus cycle
CPU
CPU
CPU
DMAC
Read
DMAC
Write
DMAC
Read
DMAC DMAC
Write Read
DMAC
Write
CPU
Figure 9.15 DMA Transfer Example in the Burst Mode
Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table 9.5
shows the relationship between request modes and bus modes by DMA transfer category.
Table 9.5 Relationship of Request Modes and Bus Modes by DMA Transfer Category
Addres
s Mode Transfer Category
Request
Mode
Dual
External device with DACK and
external memory
External
External device with DACK and
memory-mapped external device
External memory and external
memory
External memory and memory-
mapped external device
Memory-mapped external device
and memory-mapped external
device
External memory and on-chip
peripheral module
Memory-mapped external device
and on-chip peripheral module
On-chip peripheral module and on-
chip peripheral module
External
All*¹
All*¹
All*¹
All*²
All*²
All*²
Bus
Mode
B/C
Transfer Usable
Size (bits) Channels
8/16/32/128 0,1
B/C
8/16/32/128 0, 1
B/C
8/16/32/128 0 to 3*⁵
B/C
8/16/32/128 0 to 3*⁵
B/C
8/16/32/128 0 to 3*⁵
B/C*³ 8/16/32*⁴ 0 to 3*⁵
B/C*³ 8/16/32*⁴ 0 to 3*⁵
B/C*³ 8/16/32*⁴ 0 to 3*⁵
Rev. 4.00, 03/04, page 272 of 660