HD6417706 Datasheet, PDF (534/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

18.7 Port G
Port G is a 6-bit input port with the pin configuration shown in figure 18.7. Each pin has an input
pull-up MOS, which is controlled by Port G Control Register (PGCR) in PFC.
Port G
PTG5 (input) /
(input)
PTG4 (input) / AUDCK (input)
PTG3 (input) /
(input)
PTG2 (input) / TMS (input)
PTG1 (input) / TCK (input)
PTG0 (input) / TDI (input)
Figure 18.7 Port G
18.7.1 Register Description
Port G has the following register. Refer to section 23, List of Registers, for more details of the
addresses and access sizes.
• Port G data register (PGDR)
18.7.2 Port G Data Register (PGDR)
Port G data register (PGDR) is an 8-bit read register that stores data for pins PTG5 to PTG0.
PG5DT to PG0DT bit corresponds to PTG5 to PTG0 pin. When the function is general input port,
if the port is read the corresponding pin level is read.
PGDR is initialized by a power-on reset, after which the general input port function (pull-up MOS
on) is set as the initial pin function, and the corresponding pin levels are read. It retains its
previous value in standby mode and sleep mode, and in a manual reset.
Rev. 4.00, 03/04, page 488 of 660