HD6417706 Datasheet, PDF (588/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Software Standby to Manual Reset:
CKIO
Oscillation stops
Reset
*1
STATUS
Normal*⁴
Standby*³
Reset*²
Normal*⁴
Notes:
0 to 20 Bcyc*⁵
1. When software standby mode is cleared with a manual reset, the WDT does not count.
Keep
low during the PLL’s oscillation settling time.
2. Reset:
HH (STATUS1 high, STATUS0 high)
3. Standby: LH (STATUS1 low, STATUS0 high)
4. Normal: LL (STATUS1 low, STATUS0 low)
5. Bcyc:
Bus clock cycle
Figure 22.6 Software Standby to Manual Reset STATUS Output
• Timing for Canceling Sleep Mode
Sleep to Interrupt:
Interrupt request
CKIO
STATUS
Normal*²
Sleep*¹
Normal*²
Notes: 1. Sleep: HL (STATUS1 high, STATUS0 low)
2. Normal: LL (STATUS1 low, STATUS0 low)
Figure 22.7 Sleep to Interrupt STATUS Output
Rev. 4.00, 03/04, page 542 of 660