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| HD6417706 Datasheet, PDF (634/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series | |||
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24.3.5 Burst ROM Timing
T1
TB2
TB1
TB2
TB1
TB2
TB1
T2
CKIO
tAD
A25 to A4
tAD
A3 to A0
tCSD1
CSn
RD/WR
tRWD
tRSD
tRSD tAH
RD
tRDH1
tRDS
D31 to D0
tBSD
tBSD
BS
tDAKD1
DACKn
WAIT
tAD
tAD
tAH
tCSD2 tRWH
tRDH1
tRWD
tRSD
tAH
tRSD tRWH
tRDS1
tRDH1
tBSD
tBSD
tDAKD2
tWTS tWTH
Note: In the write cycle, the basic bus cycle, the basic bus cycle is performed.
tRDH1: Stipulated from the faster negate timing of CSn or RD
tAH: Stipulated from the slower negate timing of CSn, RD, or WEn
Figure 24.19 Burst ROM Bus Cycle (No Wait)
Rev. 4.00, 03/04, page 588 of 660
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