HD6417706 Datasheet, PDF (137/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

• H-UDI Reset
 Conditions: H-UDI reset command input (see section 21, User Debugging Interface (H-
UDI))
 Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC = H'A0000000.
Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are set to
1 and the interrupt mask bits (I3 to I0) are set to B'1111. The CPU and on-chip supporting
modules are initialized. For details, refer to section 23, List of Registers.
Table 4.3 Types of Reset
Type
Conditions for Transition
to Reset State
Power-on reset RESETP = Low
Manual reset RESETM = Low
H-UDI reset H-UDI reset command input
CPU
Initialized
Initialized
Initialized
Internal State
On-Chip Supporting Modules
(See register configuration in
relevant sections)
4.4.2 General Exceptions
• TLB miss exception
 Conditions: Comparison of TLB addresses shows no address match
 Operations: The virtual address (32 bits) that caused the exception is set in TEA and the
corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH
indicates the ASID at the time the exception occurred. The RC bit in MMUCR is
incremented by one when all ways are valid, or way-0 is set to the RC with top priority
when there is invalid way.
The PC and SR of the instruction that generated the exception are saved to the SPC and SSR,
respectively. If the exception occurred during a read, H'040 is set in EXPEVT; if the exception
occurred during a write, H'060 is set in EXPEVT. The BL, MD and RB bits in SR are set to 1
and a branch occurs to PC = VBR + H'0400.
To speed up TLB miss processing, the offset differs from other exceptions.
• TLB invalid exception
 Conditions: Comparison of TLB addresses shows address match but V = 0.
 Operations: The virtual address (32 bits) that caused the exception is set in TEA and the
corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH
indicates the ASID at the time the exception occurred. The way that generated the
exception is set in the RC bits in MMUCR.
The PC and SR of the instruction that generated the exception are saved in the SPC and SSR,
respectively. If the exception occurred during a read, H'040 is set in EXPEVT; if the exception
occurred during a write, H'060 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1
and a branch occurs to PC = VBR + H'0100.
Rev. 4.00, 03/04, page 91 of 660