HD6417706 Datasheet, PDF (330/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
7
CMF
0
R/(W)* Compare match flag
This flag indicates whether CMCNT and CMCOR
values have matched or not.
0: CMCNT and CMCOR values have not matched
Clearing condition: Write 0 to CMF after
reading CMF = 1
1: CMCNT and CMCOR values have matched
6
—
0
R/W Reserved
Both read and write are available. The write value
should always be 0.
5 to 2 —
0
R
Reserved
These bits always read as 0. The write value
should always be 0.
1
CKS1
0
R/W Clock select 1 and 0
0
CKS0
0
R/W These bits select the clock input to the CMCNT
from among the four internal clocks obtained by
dividing the system clock (Pφ). When the STR bit
of the CMSTR is set to 1, the CMCNT begins
incrementing with the clock selected by CKS1 and
CKS0.
00: P φ/4
01: P φ/8
10: P φ/16
11: P φ/64
Note: * The only value that can be written is 0 to clear the flag.
• Compare Match Counter (CMCNT)
The compare match counter (CMCNT) is a 16-bit register used as an up-counter.
When an internal clock is selected with the CKS1 and CKS0 bits of the CMCSR and the STR bit
of the CMSTR is set to 1, the CMCNT begins incrementing with the selected clock. When the
CMCNT value matches that of the CMCOR, the CMCNT is cleared to H'0000 and the CMF flag
of the CMCSR is set to 1.
The CMCNT0 is initialized to H'0000 by resets. It retains its previous value in standby mode.
• Compare Match Constant Register (CMCOR)
The compare match constant register (CMCOR) is a 16-bit register that sets the compare match
period with the CMCNT.
The CMCOR is initialized to H'FFFF by resets. It retains its previous value in standby mode.
Rev. 4.00, 03/04, page 284 of 660