HD6417706 Datasheet, PDF (107/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

3.3.2 TLB Indexing
The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits 16
to 12 and ASID bits in PTEH 4 to 0 are used as the index number regardless of the page size. The
index number can be generated in two different ways depending on the setting of the IX bit in
MMUCR.
1. When IX = 0, VPN bits 16 to 12 alone are used as the index number
2. When IX = 1, VPN bits 16 to 12 are EX-ORed with ASID bits 4 to 0 to generate a 5-bit index
number
The second method is used to prevent lowered TLB efficiency that results when multiple
processes run simultaneously in the same virtual address space (multiple virtual memory) and a
specific entry is selected by indexing of each process. Figures 3.5 and 3.6 show the indexing
schemes.
Virtual address
31
17 16 12 11
Index
PTEH register
0
31
10 7
0
VPN
0 ASID
Exclusive-OR
ASID(4 to 0)
Ways 0 to 3
0 VPN(31–17) VPN(11–10) ASID(7–0) V PPN(3–0) PR(1–0) SZ C D SH
31
Address array
Data array
Figure 3.5 TLB Indexing (IX = 1)
Virtual address
31
17 16 12 11
0
Index
Ways 0 to 3
0 VPN(31–17) VPN(11–10) ASID(7–0) V PPN(31–10) PR(1–0) SZ C D SH
31
Address array
Data array
Figure 3.6 TLB Indexing (IX = 0)
Rev. 4.00, 03/04, page 61 of 660