HD6417706 Datasheet, PDF (230/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
2
RFSH
0
R/W Refresh Control
The RFSH bit determines whether or not the
refresh operation of the DRAM and synchronous
DRAM is performed. The timer for generation of
the refresh request frequency can also be used as
an interval timer.
0: No refresh
1: Refresh
1
RMODE 0
R/W Refresh Mode
The RMODE bit selects whether to perform an
ordinary refresh or a self-refresh when the RFSH
bit is 1. When the RFSH bit is 1 and this bit is 0, a
CAS-before-RAS refresh or an auto-refresh is
performed on synchronous DRAM at the period
set by the refresh-related registers RTCNT,
RTCOR and RTCSR. When a refresh request
occurs during an external bus cycle, the bus cycle
will be ended and the refresh cycle performed.
When the RFSH bit is 1 and this bit is also 1, the
synchronous DRAM will wait for the end of any
executing external bus cycle before going into a
self-refresh. All refresh requests to memory that is
in the self-refresh state are ignored.
0: CAS-before-RAS refresh (RFSH must be 1)
1: Self-refresh (RFSH must be 1)
0
—
0
R/W Reserved
This bit is always read as 0. The write value
should always be 0.
Rev. 4.00, 03/04, page 184 of 660