HD6417706 Datasheet, PDF (290/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

• Three types of Transfer requests
 External request: From two DREQ pins (channels 0 and 1 only). DREQ can be detected
either by the falling edge or by the low level.
 On-chip module request: Requests from on-chip peripheral modules such as serial
communications interface (SCIF), A/D converter (A/D), and a timer (CMT). This request
can be accepted in all the channels.
 Auto request: The transfer request is generated automatically within the DMAC.
• Selectable bus modes: Cycle-steal mode or burst mode
• Selectable channel priority levels
 Fixed mode: The channel priority is fixed.
 Round-robin mode: The priority of the channel in which the execution request was
accepted is made the lowest.
• Interrupt request: An interrupt request can be generated to the CPU after transfers end by the
specified counts.
On-chip
peripheral
module
,
SCIF
A/D converter
CMT
DEI_n
DACK0, DACK1
DRAK0, DRAK1
External
ROM
External
RAM
External I/O
(memory
mapped)
External I/O
(with
acknowledge)
Interation
control
DMAC module
SAR_n
Register
control
Start-up
control
DAR_n
DMATCR_n
CHCR_n
Request
priority
control
DMAOR
Bus interface
Bus state
controller
Legend
DMAOR: DMAC operation register
SAR_n: DMAC source address register
DAR_n: DMAC destination address register
DMATCR_n:DMAC transfer count register
CHCR_n: DMAC channel control register
DEI_n: DMA transfer-end interrupt request to
CPU
n:
0 to 3
Figure 9.1 DMAC Block Diagram
Rev. 4.00, 03/04, page 244 of 660