HD6417706 Datasheet, PDF (203/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

4. The change of a UBC register value is executed in MA (memory access) stage. Therefore,
even if the break condition matches in the instruction fetch address following the instruction in
which the pre-execution break is specified as the break condition, no break occurs. In order to
know the timing UBC register is changed, read the last written register. Instructions after then
are valid for the newly written register value.
5. The branch instruction should not be executed as soon as PC trace register BRSR and BRDR
are read.
6. When PC breaks and TLB exceptions or errors occur in the same instruction. The priority is as
follows:
A. Break and instruction fetch exceptions: Instruction fetch exception occurs first.
B. Break before execution and operand exception: Break before execution occurs first.
C. Break after execution and operand exception: Operand exception occurs first.
Rev. 4.00, 03/04, page 157 of 660