HD6417706 Datasheet, PDF (17/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Item
19.4 Bus Master Interface
Figure 19.2 A/D Data
Register Access Operation
(Reading H'AA40)
Page
502
Revision (See Manual for Details)
Figure 19.2 amended
Lower byte read
CPU
(H'40)
Bus
interface
Module internal data bus
TEMP
(H'40)
19.6.3 Scan Mode (MULTI = 507
1, SCN = 1)
Figure 19.7 Example of A/D
Converter Operation (Scan
Mode, Channels AN0 to AN2
Selected)
19.6.4 Input Sampling and 508
A/D Conversion Time
Upper byte of
A/D data register
(H'AA)
Lower byte of
A/D data register
(H'40)
Figure 19.7 amended
Set*¹
Clear*¹
ADDRA*² ADDRB*² ADDRC*² ADDRD*²
Notes: 1. Downward arrows indicate instruction executed by
software.
2. Data is ignored during conversion.
Description deleted
In multi mode and scan mode, the values given in table 19.3 apply to
the first conversion. In the second and subsequent conversions the
conversion time is fixed at 512 states when CKS = 0 or 256 states
when CKS = 1.
19.9.1 Setting Analog Input 511
Voltage
21.3.3 Boundary Scan
522
Register (SDBSR)
Table 21.2 This LSI's Pins
and Boundary Scan Register
Bits
21.4.1 TAP Controller
525
Description amended
• Analog Input Voltage Range: During A/D conversion, the voltages
input to the analog input pins ANn should be in the range AVSS ≤
ANn ≤ AVCC (n = 0 to 3).
• AVCC, Avss, Input Voltage: AVcc and AVss should be related as
follows: AVcc = VccQ ± 0.2 V and AVss = Vss.
Table 21.2 amended
Bit 171 I/O
(Before) (blank) → (After) OUT
Bit 160 I/O
(Before) OUT → (After) Control
Note amended
Note: … The TDO is at high impedance, except with shift-DR (shift-
SR) and shift-IR states. When TRST = 0, there is a transition to test-
logic-reset asynchronously with TCK.
Rev. 4.00, 03/04, page xvii of xlvi