HD6417706 Datasheet, PDF (533/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

18.6.1 Register Description
Port F has the following register. Refer to section 23, List of Registers, for more details of the
addresses and access sizes.
• Port F data register (PFDR)
18.6.2 Port F Data Register (PFDR)
Port F data register (PFDR) is an 8-bit register composed of a 1-bit readable register and a 7-bit
readable/writable register. This register stores data for pins PTF6 to PTF0. PF6DT to PF0DT bit
corresponds to PTF6 to PTF0 pin. When the function is general input port, if the port is read the
corresponding pin level is read.
PFDR is initialized by a power-on reset, after which the general input port function (pull-up MOS
on) is set as the initial pin function, and the corresponding pin levels are read. It retains its
previous value in standby mode and sleep mode, and in a manual reset.
Bit
Bit Name Initial Value R/W Description
7

0
R Reserved
6
PF6DT 0
R/W Table 18.6 shows the function of PFDR.
5
PF5DT 0
R/W
4
PF4DT 0
R/W
3
PF3DT 0
R/W
2
PF2DT 0
R/W
1
PF1DT 0
R/W
0
PF0DT 0
R/W
Table 18.6 Read/Write Operation of the Port F Data Register (PFDR)
PFnMD1 PFnMD0 Pin State
Read
0
0
Other functions PFDR value
1
1
0
1
Output
Input (Pull-up
MOS: on)
Input (Pull-up
MOS: off)
PFDR value
Pin state
Pin state
Write
Can be written to PFDR but does not affect
the pin state.
A value to be written is output from the pin.
Can be written to PFDR but does not affect
the pin state.
Can be written to PFDR but does not affect
the pin state.
(n = 0 to 6)
Rev. 4.00, 03/04, page 487 of 660