HD6417706 Datasheet, PDF (539/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

18.10 SC Port
SC port is a 3-bit I/O, 2-bit output and 4-bit input port with the pin configuration shown in figure
18.10. Each pin has an input pull-up MOS, which is controlled by SC port Control Register
(SCPCR) in PFC.
SC Port
SCPT5 (input) /
(input) / IRQ5 (input)
SCPT4 (I/O) /
(output)
SCPT3 (I/O) / SCK2 (I/O)
SCPT2 (input) / RxD2 (input)
SCPT2 (output) / TxD2 (output)
SCPT1 (I/O) / SCK0 (I/O)
SCPT0 (input) / RxD0 (input)
SCPT0 (output) / TxD0 (output)
Figure 18.10 SC Port
18.10.1 Register Description
Port SC has the following register. Refer to section 23, List of Registers, for more details of the
addresses and access sizes.
• SC Port data register (SCPDR)
18.10.2 SC Port Data Register (SCPDR)
SC Port data register (SCPDR) is a 5-bit read/write and 3-bit read register that stores data for pins
SCPT5 to SCPT0. SCP5DT to SCP0DT bit corresponds to SCPT5 to SCPT0 pin. When the pin
function is general output port, if the port is read, the value of the corresponding SCPDR bit is
returned directly. When the function is general input port, if the port is read, the corresponding pin
level is read.
SCPDR is initialized to B'***00000 by a power-on reset. After initialization, the general input
port function (pull-up MOS on) is set as the initial pin function, and the corresponding pin levels
are read from bits SCP5DT to SCP3DT and SCP1DT. SCPDR retains its previous value in
standby mode and sleep mode, and in a manual reset.
Note that the low level is read if bit 7 is read except in general-purpose input.
When reading the state of the RxD2 and RxD0 pins of the SCP2DT and SCP0DT bits in SCPDR
without clearing the TE or RE bit in SCSCR to 0, set the RE bit in SCSCR to 1. When the RE bit
is set to 1, the RxD pin is for input and the pin state can be read before the setting of SCPCR.
Rev. 4.00, 03/04, page 493 of 660