HD6417706 Datasheet, PDF (500/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Error processing
No
ER = 1?
Yes
Receive error processing
No
BRK= 1?
Break processing
1. Whether a framing error or parity error has
occurred in the receive data read from
SCFRDR2 can be ascertained from the FER
and PER bits in SCSSR2.
2. When a break signal is received, receive data
is not transferred to SCFRDR2 while the BRK
flag is set. However, note that the last data in
SCFRDR2 is H'00 and the break data in which
a framing error occurred is stored.
No
DR= 1?
Yes
Read receive data in SCFRDR2
Clear DR, ER, BRK flags in
SCSSR2 to 0
End
Figure 16.10 Sample Serial Reception Flowchart (2)
In serial reception, the SCIF operates as described below.
1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal
synchronization and starts reception.
2. The received data is stored in SCRSR2 in LSB-to-MSB order.
3. The parity bit and stop bit are received.
After receiving these bits, the SCIF carries out the following checks.
A. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only
the first is checked.
B. The SCIF checks whether receive data can be transferred from the receive shift register
(SCRSR2) to SCFRDR2.
C. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not
set.
If all the above checks are passed, the receive data is stored in SCFRDR2.
Note: Reception is not suspended when a receive error occurs.
Rev. 4.00, 03/04, page 454 of 660