HD6417706 Datasheet, PDF (324/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

1st sampling
CKIO
DRAK
(High active)
Bus cycle
DACK
CPU
DMAC(Read)
DMAC(Write)
DMAC(Read)
DMAC(Write)
DMAC(Read)
Figure 9.23 Burst Mode, Edge Input
9.4.6 Source Address Reload Function
Channel 2 includes a reload function, in which the value returns to the value set in the SAR_2 for
each four transfers by setting the RO bit in CHCR_2 to 1. 16-byte transfer cannot be used. Figure
9.24 shows this operation. Figure 9.25 shows the timing chart of the source address reload
function, which is under the following conditions: burst mode, auto request, 16-bit transfer data
size, SAR_2 count-up, DAR_2 fixed, reload function on, and usage of only channel 2.
Transfer
request
DMAC
DMAC control
Reload control
4 time
count
RO bit = 1
Count signal
Reload signal
Reload
signal
CHCR_2
DMATCR_2
SAR_2
(initial value)
SAR_2
Figure 9.24 Source Address Reload Function Diagram
Rev. 4.00, 03/04, page 278 of 660