HD6417706 Datasheet, PDF (189/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
20
BASMB 0
R/W Break ASID Mask B
Specifies whether the bits of channel B break ASID7
to ASID0 (BASB7 to BASB0) set in BASRB are
masked or not.
0: All BASRB bits are included in break condition,
ASID is checked
1: No BASRB bits are included in break condition,
ASID is not checked
19 to 16 —
All 0
R Reserved
These bits are always read as 0. The write value
should always be 0.
15
SCMFCA 0
R/W CPU Condition Match Flag A
When the CPU bus cycle condition in the break
conditions set for channel A is satisfied, this flag is set
to 1 (not cleared to 0). In order to clear this flag, write
0 into this bit.
0: The CPU cycle condition for channel A does not
match
1: The CPU cycle condition for channel A matches
14
SCMFCB 0
R/W CPU Condition Match Flag B
When the CPU bus cycle condition in the break
conditions set for channel B is satisfied, this flag is set
to 1 (not cleared to 0). In order to clear this flag, write
0 into this bit.
0: The CPU cycle condition for channel B does not
match
1: The CPU cycle condition for channel B matches
13
SCMFDA 0
R/W DMAC Condition Match Flag A
When the on-chip DMAC bus cycle condition in the
break conditions set for channel A is satisfied, this
flag is set to 1 (not cleared to 0). In order to clear this
flag, write 0 into this bit.
0: The DMAC cycle condition for channel A does not
match
1: The DMAC cycle condition for channel A matches
Rev. 4.00, 03/04, page 143 of 660