HD6417706 Datasheet, PDF (256/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

The example in figure 8.13 shows the basic timing. To connect low-speed synchronous DRAM,
the cycle can be extended by setting WCR2 and MCR bits. The number of cycles from the ACTV
command output cycle, Tr, to the READ command output cycle, Tc1, can be specified by the
RCD bit in MCR, with a values of 0 to 3 specifying 1 to 4 cycles, respectively. In case of 2 or
more cycles, a Trw cycle, in which an NOP command is issued for the synchronous DRAM, is
inserted between the Tr cycle and the Tc cycle. The number of cycles from READ and READA
command output cycles Tc1-Tc4 to the first read data latch cycle, Td1, can be specified as 1 to 3
cycles independently for areas 2 and 3 by means of A2W1 and A2W0 or A3W1 and A3W0 in
WCR2. This number of cycles corresponds to the number of synchronous DRAM CAS latency
cycles.
Tr
CKIO
Address
upper bits
A12 or A11 ^*1
Address
lower bits*²
or
Tc1
Tc2/Td1
Tc3/Td2
Tc4/Td3
Td4
Tpc
RD/
D31 to D0
Notes: 1. Command bit
2. Column address
Figure 8.13 Basic Timing for Synchronous DRAM Burst Read
Rev. 4.00, 03/04, page 210 of 660